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Google 下一代 TPU 将采用 Intel EMIB-T 封装，替代 TSMC CoWoS
AI 推荐理由
首次主流 AI 训练加速器从 TSMC CoWoS 转向 Intel EMIB-T，EMIB-T 的技术细节和量产进展值得持续跟踪，可能影响 AI 芯片封装格局。核心解读
Google 下一代 TPU（代号 Humufish）将采用 Intel 的 EMIB-T 封装技术，取代业界默认的 TSMC CoWoS。EMIB-T 在桥接器中加入 TSV、电容和接地层，可支持下一代 HBM 和高带宽互连，但量产良率和进度是关键风险。
全文
Google's next TPU, codenamed Humufish, is set to use Intel's EMIB-T instead of TSMC CoWoS.
Nearly every leading AI training accelerator today is packaged on a TSMC 2.5D flow, and almost all of it is CoWoS. CoWoS is the industry default, which is exactly why a flagship part moving off it is worth attention.
The core difference. CoWoS places all dies on a single large silicon/RDL interposer. EMIB embeds small silicon bridges directly in the organic substrate, only where die-to-die links are needed. (1/4)🧵
SemiAnalysis (@SemiAnalysis_): Humufish is using EMIB-T. The "T" is TSV. Plain EMIB has no vias in the bridge, so power has to detour around it through the substrate, which strains power delivery. EMIB-T sends power vertically straight through the bridge, with added capacitors and a ground plane for cleaner power. That is what makes it ready for next-gen HBM and higher-bandwidth interconnects. (3/4)
SemiAnalysis (@SemiAnalysis_): The risk. Plain EMIB has shipped in volume for years, but EMIB-T is new, and a power-delivering bridge is harder to manufacture at scale. The upside only lands if Intel can ramp yield and volume on schedule. If it slips, the fallback is the same capacity-constrained CoWoS this was meant to avoid. Compelling architecture. Execution is the question. (4/4)